1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a pulse signal generation circuit for adjusting a pulse width of an input pulse signal and outputting an output pulse signal having the changed pulse width.
2. Description of the Related Art
A semiconductor memory device, such as double data rate synchronous DRAM (DDR SDRAM), includes a variety of internal circuits for performing a variety of operations. One of the internal circuits is a pulse signal generation circuit for generating a pulse signal.
FIG. 1 is a circuit diagram of a conventional pulse signal generation circuit.
Referring to FIG. 1, the pulse signal generation circuit includes a delay unit 110 and an output unit 120.
The delay unit 110 incorporates a predetermined amount of delay into an input pulse signal SIG_IN and outputs a delayed signal. The amount of delay incorporated by the delay unit 110 is one of important factors that determine a pulse width of an output pulse signal SIG_OUT. The output unit 120 generates the output pulse signal SIG_OUT in response to a signal SIG_A inverted from the input pulse signal SIG_IN and the signal SIG_B from the delay unit 110.
FIG. 2 is a timing diagram illustrating the operation of the pulse signal generation circuit of FIG. 1, where the amount of delay of the delay unit 110 is indicated by ‘DY’.
Referring to FIGS. 1 and 2, the delay unit 110 delays the input pulse signal SIG_IN by the amount of delay DY and outputs the signal ‘SIG_B’. The output pulse signal SIG_OUT is generated in response to the signal ‘SIG_A’ and the signal ‘SIG_B’. As can be seen from the figure, the pulse width of the output pulse signal SIG_OUT is equal to the pulse width of the input pulse signal SIG_IN plus the amount of delay DY.
With the recent development of the process and design technologies of semiconductor memory devices, a semiconductor memory device operates at a very high speed, which requires a clock signal having a high frequency. This means that the pulse width of the clock signal needs to become smaller. A clock signal provides a reference in the operation to a semiconductor memory device. That is, a semiconductor memory device internally generates a pulse signal with reference to the pulse width of a clock signal.
As described above, as the pulse width of a clock signal becomes smaller, the pulse width of a pulse signal becomes smaller. Accordingly, the following concerns arise.
According to prior art, for generation of a pulse signal, the amount of delay DY of the delay unit 110 has to be smaller than the pulse width of the input pulse signal SIG_IN. If the amount of delay DY of the delay unit 110 is greater than the pulse width of the input pulse signal SIG_IN, the output pulse signal SIG_OUT has two pulses. For this reason, the amount of delay DY must be designed very precisely for generation of the pulse signal as the pulse width of a clock signal becomes smaller.
However, the design of a pulse signal generation circuit is becoming more difficult because an influence due to a PVT (process, voltage, and temperature) and a gradual decrease in the pulse width of the input pulse signal SIG_IN should be reflected to a design of an inverter chain in the delay unit.